1. Technical Field
The present invention relates generally to electronic packaging, and more particularly, to an organic semiconductor chip carrier and method of forming the same.
2. Related Art
As the demand grows in the industry for miniaturized high performance semiconductor packages, the need to manufacture a reliable device having high density connections becomes increasingly important. In other words, producing a device having the largest number of chip connections over the smallest possible area is one of the primary objectives. It is also important to produce a structure capable of providing adequate xe2x80x9cwireoutxe2x80x9d capabilities to take advantage of the high density connections.
FIG. 1 shows a cross-sectional view of a related art semiconductor chip carrier 10. The carrier 10 includes a ground plane 12, a first dielectric layer 14 on each side of the ground plane 12, a signal layer 16 over each first dielectric layer 14, a second dielectric layer 18 over each signal layer 16, a power core 20 over each second dielectric layer 18, and a third dielectric layer 22 over each power core 20. The carrier 10 has a plurality of copper plated through holes 24, wherein the copper plating forms a xe2x80x9cdogbonexe2x80x9d connection pad 28 on the surface of the carrier 10. A redistribution layer 30 covers the surface of the carrier 10. The redistribution layer 30 contains contact areas 34, which facilitate electrical connection of semiconductor chips (not shown), through interconnections (also not shown), to the dogbone connection pads 28 of the plated through holes 24.
FIG. 2 shows a top view of the related art semiconductor chip carrier 10. The dogbone connection pads 28 consume a large portion of the surface area on the carrier 10. This is because the interconnection contact area 34, the area upon which the interconnection is mounted, is offset from the plated through hole 24. As a result, the density of plated through holes 24 and interconnections for each carrier 10 is limited.
Additionally, due to differences in the coefficient of thermal expansion between the chip carrier, the chips and the interconnections therebetween, internal stresses develop within the semiconductor package during thermal cycling, which may eventually lead to device failure.
As a result, there exists a need in the industry for a more reliable, compact semiconductor device.
The present invention provides a more reliable semiconductor chip carrier, having high density plated through hole spacing and chip connections, and a method of forming the same.
The first general aspect of the present invention provides an interconnect structure comprising: a substrate; a plated through hole positioned within the substrate; a redistribution layer on a first and a second surface of the substrate; and a via within the redistribution layer, selectively positioned over and electrically connecting the plated through hole. This aspect allows for a semiconductor chip carrier having an increased plated through hole and chip connection density. This aspect provides vias, containing chip connection pads therein, positioned directly over the plated through holes, which eliminate the conventional dogbone construction. This aspect also provides additional wireout capabilities to take advantage of the increased plated through hole and chip connection density, namely, an additional pair of signal planes and an additional pair of power planes. This aspect also provides a redistribution layer which is made fatigue resistant due to the material choice, as well as locating the second pair of power planes directly underneath the redistribution layer. Due to the roughened surface of the second pair of power planes, the adhesion strength of the redistribution layer to the underlying substrate is increased. In addition, the second pair of power planes act as a redundant layer, preventing cracks originating within the redistribution layer from propagating through the carrier. Furthermore, this aspect provides for direct via connections, which eliminate the need for plated through holes.
A second general aspect of the present invention provides a method of forming a semiconductor chip carrier, comprising the steps of: providing a substrate, having a plated through hole therein; depositing a redistribution layer on a first and a second surface of the substrate; and forming a via within the redistribution layer, selectively positioned over and electrically contacting the plated through hole. This aspect provides a method of forming a semiconductor chip carrier having similar advantages as those associated with the first aspect.
A third general aspect of the present invention provides a semiconductor chip carrier comprising: a substrate having a plated through hole therein; and a fatigue resistant redistribution layer on a first and second surface of the substrate. This aspect provides similar advantages as those associated with the first aspect.
The foregoing and other features of the invention will be apparent from the following more particular description of the embodiments of the invention.